1. Field of the Invention
The present invention relates to a semiconductor device including plural electrode pads.
2. Description of the Related Art
A DRAM (Dynamic Random Access Memory) as a type of a memory device includes a cell block in which plural memory cells are arranged and a sense amplifier that amplifies signal indicating information stored in one memory cell selected out of the plural memory cells. Plural electrode pads (hereinafter simply referred to as pads) connected to internal circuits such as the cell block and the sense amplifier are provided on a chip surface of the memory device.
As an example of a package of a semiconductor device including a chip of a memory device, there is a package having a configuration in which pads are connected to bond fingers via wires by wire bonding and the bond fingers are connected to solder balls equivalent to external terminals. The wires that connect the pads and the bond fingers may be called bonding wires to distinguish the wires from a metal wire in the chip. However, in this specification, the wires are simply referred to as wires.
As the pads, there are plural kinds of pads depending on their purposes. A part of the plural kinds of pads is explained below. As the pads, there are a pad for address selection (hereinafter referred to as ADD pad) that receives input of an address signal for selecting one of plural memory cells in a cell block from the outside, a pad for input/output of data (hereinafter referred to as DQ pad), and a pad for sense amplifier ground potential (hereafter referred to as VSSSA pad) as a pad for supplying ground potential voltage (VSSSA) to a sense amplifier. The ADD pad and the DQ pad belong to the category of a signal pad as a pad for at least receiving the input of a signal from the outside of a semiconductor device or for outputting a signal to the outside.
An example of a semiconductor laminate package is disclosed in JP2009-038142A (hereinafter referred to as Patent Document 1). In a chip disclosed in this document, plural pads are arranged side by side in a longitudinal direction of the chip near the center of the chip. The pads are connected to a connection land or a wire expanding portion via wire lines.
When wire bonding is performed in the same direction from the pads of a pad row with the pad row as a reference, the wires respectively connected to the pads adjacent to each other are provided in parallel spaced apart from each other by the distance of a pad interval. When the VSSSA pad is arranged next to the DQ pad, a first wire connected to the VSSSA pad and a second wire connected to the DQ pad extend in parallel spaced apart from each other by the distance of the pad interval.
When noise is caused in the first wire by potential fluctuation in VSSSA, since the first wire and the second wire extend in parallel at the distance of the pad interval, in some case, the noise is propagated to the second wire. In this case, a signal input via the DQ pad is adversely affected. When timing of the occurrence of the noise in the first wire and timing of the input of the signal to the DQ pad coincide with each other, a memory device is likely to misrecognize a high level of a DQ signal as a low level or misrecognize the low level as the high level.
In the technique disclosed in Patent Document 1, a pad for DQ voltage for ground potential (equivalent to a VSSQ pad) is arranged next to a pad for DQ signal. The direction where the wire line is connected to the pad for DQ signal at a position near the chip center is in the opposite direction to the direction where the wire line is connected to the VSSQ pad also at the position near the chip center. However, Patent Document 1 does not disclose that the VSSSA pad is arranged next to the pad for DQ signal.